Performance Analysis of Combinatorial Digital Circuit Evolution with Cluster Growth Technique

An interesting approach of using genetic programming is to synthesize circuit with least possible number of logic gates and the same is presented in this paper. The genetic algorithm (GA) is one of the optimization techniques of evolutionary algorithm used to design evolvable hardware. This paper proposes the applicability of cluster based growth approach with genetic programming. Since in previous related literature of evolvable hardware the drawback stated is scalability, evolution time and redundancy. With Clustering technique presented in this paper there is an effort to overcome these drawbacks. The method of evolution is also modified so that the evolution time is reduced. Since in this paper the clustering evolution is used that reduces the size of chromosome in genotype and this somewhat over comes the problem of scalability. Our main contributions are: 1) Adaptation of genetic operators in a way suitable for clustering growth, 2) Clustering with genetic programming of digital circuits and show its performance, 3) To obtain the desired functionality with least number of logic gates such that the interconnection of nodes in the earlier defined architecture is modified with clustering, so that the fast convergence is obtained. This in turn reduces stalling effect in evolvable hardware.